ITC-CSCC 2023

June 25(Sun) – 28(Wed) / Grand Hyatt Jeju, Republic of Korea

Program

Important Dates
  • Submission of Paper
    April 14, 2023April 21, 2023
  • Notification of Acceptance
    May 8, 2023
  • Submission of Final Paper
    May 22, 2023

TODAY 2024. 05. 03

ITC-CSCC 2023

D-0

Plenary Speakers

Innovations in Flash NAND development and AI utilization fields

Presenter

Dr. Ki-Whan Song

  • Corporate EVP of SAMSUNG Electronics

Abstract

Through the great innovations, Flash NAND devices have played an important role in mass data storage and computing systems. We will review the major innovations and forecast the mega trend for the future. In addition, We will introduce the AI utilization in the design and manufacturing fields.

Education :
2005/1996/1994 Ph.D./M.S./B.S E.E., Seoul National University

Career :
2022 Advanced Flash Technology Development Team
2020 Flash Product Engineering Team
2011 Flash Design Team
2005 Advanced Technology Development Team
1996 DRAM Design Team


Hardware Security and Safety of IC Chips

Presenter

Prof. Makoto Nagata

  • Kobe University

Abstract

IC chips are key enablers to a smartly networked society and need to be more compliant to security and safety. Semiconductor solutions for autonomous vehicles must meet stringent regulations and requirements. While designers develop circuits and systems to meet the performance and functionality of such products, countermeasures are proactively implemented in silicon to protect against harmful disturbances and even intentional adversarial attacks.
This talk will start with Electromagnetic Compatibility (EMC) techniques applied to IC chips for safety to motivate EMC-aware design, analysis, and implementation. It will then discuss IC design challenges to achieve higher levels of hardware security (HWS). Crypto-based secure IC chips are investigated to avoid the risks of side-channel leakages and side-channel attacks, corroborated with silicon demonstrating analog techniques to protect digital functionality. The EMC and HWS disciplines derived from electromagnetic principles are key to establishing IC design principles for security and safety.

Makoto Nagata received the B.S. and M.S. degrees in physics from Gakushuin University, Tokyo, Japan, in 1991 and 1993, respectively, and the Ph.D. degree in electronics engineering from Hiroshima University, Hiroshima, Japan, in 2001. He is currently a Dean and Professor with the Graduate School of Science, Technology and Innovation, Kobe University. His research interests include design techniques targeting high-performance mixed analog, RF and digital VLSI systems with particular emphasis on power/signal/substrate integrity and electromagnetic compatibility, testing and diagnosis, three-dimensional system integration, as well as their applications for hardware security and safety, and cryogenic electronics for quantum computing. Dr. Nagata is a Senior Member of IEEE and IEICE. He has been a member of a variety of technical program committees of international conferences such as International Solid-State Circuits Conference and Symposium on VLSI Circuits.


Signal Detection Evolution in Ultra High-Density Magnetic Recording

Presenter

Prof. Piya Kovintavewat

  • Nakhon Pathom Rajabhat University, Thailand

Abstract

Currently, a hard disk drive using a perpendicular recording technology is approaching its storage limit at 1 tera bits per square inch (Tb/in2) due to the super-paramagnetic effect. Many recording technologies have been proposed to overcome this limit, such as bit-patterned magnetic recording (BPMR), two-dimensional magnetic recording (TDMR), and multi-layer magnetic recording (MLMR). However, this talk will focus only on BPMR because it can now be deployed in a commercial market and can achieve the storage capacity up to 4 Tb/in2. This talk summarizes the sophisticated signal detection techniques used in BPMR such as 2D coding, multi-head multi-track detection, and Al-based data detection.

Dr. Piya Kovintavewat received the B.Eng. summa cum laude from Thammasat University, Thailand (1994), the M.S. degree from Chalmers University of Technology, Sweden (1998), and the Ph.D. degree from Georgia Institute of Technology (2004), all in Electrical Engineering.
He is currently a Professor in Electrical Engineering Program, Faculty of Science and Technology, Nakhon Pathom Rajabhat University (NPRU), Nakhon Pathom, Thailand. His main research interests include coding and signal processing as applied to digital data storage systems.
Prior to working at NPRU, he worked as an engineer at Thai Telephone and Telecommunication company (1994-1997), and as a research assistant at National Electronics and Computer Technology Center (1999), both in Thailand. He also had work experiences with Seagate Technology, Pennsylvania, USA (summers 2001, 2002, and 2004).


Re-defining AI: Towards neuro-SW/HW Architectures

Presenter

Dr. Kamran Eshraghian

  • President iDataMap Corporation

Abstract

How does a coder/architect perceive AI? During the last sixty years the insight gained into the gap between functional Artificial Intelligence (as we know it today) and Artificial General Intelligence (AGI) highlights the unfathomable challenges encountered by circuits and systems architects in their quest for new pathways towards implementation of ‘Reason, Learn, and Plan’ design paradigm – the Holy Grail of future HW/SW neuromorphic architectures (c.f. GPT5, SpikeGPT). Functionalities of AI that we have become accustomed is identical with Extended Intelligence (EI). To alleviate the ambiguities it seems logical to redefine AI within EI domain and link the two with a ‘Gap Function’ G(w) matrix characterized by collective behavior of Cognitive, Emotional and Spiritual derived parameters where feasible. Very likely the building primitive in emerging architectures is basic element, the neuro-logic block (c.f. VLSI philosophy) that must cope with demands on power consumption, running cost, and CO2 foot-print. The insight into neuro-HW/SW complexities together with the decision matrix (derived from e.g., reductionism, consciousness, mirror-neurons, Qbit, and Limits) as an extension to our neuro-processing capability is likely to be a new design cockpit (yet to be defined) when venturing into upcoming SW/HW co-design, thus paving the way towards the inevitable 5th Industrial Revolution.

Kamran Eshraghian received his MEngSc. and Ph.D. from University of Adelaide, South Australia in 1977 and 1980 respectively, and 2004 was awarded Dr-Ing e.h. from University of Ulm, Germany. He is best known as one of the fathers of CMOS VLSI having influenced two generations of researchers and developers. Currently he is the executive chairman and president of iDataMap Corporation with a focus on digital healthcare and predictive medicine. In 1979 he joined the Department of Electrical and Electronic Engineering, University of Adelaide. Subsequently in 1995 as Distinguished Professor and School Chair he led the School of Computer and Communication Engineering and Mathematics in Western Australia. In 2005 as Founder/President of ELabs he formulated new concepts for integration of nanoelectronics with those of bio and photon-based technologies. In 2007 he became the inaugural holder of Ferrero Family Chair in Electrical Engineering at University of California, Merced with focus on memristor driven architectures and SoS integration prior to his involvement with Korea’s World Class University program at CBNU. His current research interest includes neurologic-SW/HW within the computational neuroscience domain. Prof Eshraghian is a Fellow and life member of IEAust